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A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs
| Title | A high-gain, high-speed parametric residue amplifier for SAR-assisted pipeline ADCs |
| Publication Type | Conference Paper |
| Year of Publication | 2016 |
| Authors | c Bahubalindruni PG a, Goes J b, Barquinha P c |
| Conference Name | 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2016 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| ISBN Number | 9781509004904 |
| Keywords | 65 nm CMOS technologies, Amplification, Amplifiers (electronic), High gain, High Speed, Industrial requirements, Integrated circuit manufacture, Operating frequency, Parametric amplification, Parametric amplifiers, Pipeline ADCs, Pipelines, Reconfigurable hardware, Residue amplification |
| Abstract | This paper presents a high-speed and high-gain dynamic residue amplifier for two-stage SAR-assisted pipeline ADC. Parametric amplification technique is incorporated in the residue amplifier to enhance the gain, in order to meet the industrial requirements of the residue amplifier of an ADC with ENOB ≥ 10.5 bits. From simulations the proposed circuit has shown a gain of 22.05 dB and a power consumption of 0.31 mW, at an operating frequency of 1.75 GHz when VDD is 1.2 V and CL is 150 fF in a standard 65 nm CMOS technology. © 2016 IEEE. |
| URL | https://www.scopus.com/inward/record.uri?eid=2-s2.0-84983780977&doi=10.1109%2fSMACD.2016.7520732&partnerID=40&md5=d1a0c7ec842a6ada7cc03638a6c993df |
| DOI | 10.1109/SMACD.2016.7520732 |
